High Performance, Variable-Length Instruction Encodings

Minimizing program code size reduces power consumption and space, which is especially important in embedded systems. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This thesis presents a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performance processors. The new headsand-tails (HAT) format splits each instruction into a fixed-length head and a variable-length tail, and packs heads and tails in separate sections within a larger fixed-length instruction bundle. The heads can be easily fetched and decoded in parallel as they are a fixed distance apart in the instruction stream, while the variable-length tails provide improved code density. Compared to earlier schemes that expand compressed formats on cache refills, the new format is suitable for direct execution from the instruction cache, thereby increasing effective cache capacity and reducing cache power. Various implementations of the HAT format have been evaluated on re-encoded RISC and VLIW instruction sets, yielding compression ratios between 60% and 75% using only simple statistical compression techniques. Thesis Supervisor: Krste Asanović Title: Assistant Professor